Re:LM3S6965 crashes in hibernate
I think I've found something. In the ARM v7m reference manual, I see this description:
A6.7.42 LDR (immediate)
Load Register (immediate) calculates an address from a base register value and an immediate offset, loads
a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing.
See Memory accesses on page A6-15 for information about memory accesses.
The register loaded can be the PC. If it is, the word loaded for the PC is treated as an address or exception
return value and a branch occurs. Bit<0> complies with the ARM architecture interworking rules for
branches to Thumb state execution and must be 1. If bit<0> is 0, a UsageFault exception occurs.
The disassembler shows this:
| Code: |
HibernateClockSelect:
00000178 4904 LDR R1, [PC, #0x10]
0000017A 2304 MOVS R3, #0x4
0000017C E000 B ?Subroutine0
0000017E 0000 MOVS R0, R0
?Subroutine0:
00000180 680A LDR R2, [R1] <<<<<
00000182 439A BICS R2, R2, R3
00000184 4302 ORRS R2, R2, R0
00000186 600A STR R2, [R1]
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LDR R2, [R1] compiles as 0x680A, where Bit<0> == 0, and the book says this causes a UsageFault, which escalates to a HardFault - ehich is where the code ends up.
Have I found something unique, or is there a mundane explanation for this?
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