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wella

Platinum Boarder

2008/09/25 05:06

interrupts 6 cycles

Hi,

does anybody know why exactly 6 cycles before new ISR is being serviced in case of tail-chaining or pop-preemption?

Martin

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LMI Dave

Platinum Boarder

2008/09/25 08:25

Re:interrupts 6 cycles

Martin,

If an exception handler ends and another exception is already pending that has a higher priority than any of the exceptions currently stacked (nested), the CPU tail-chains to the new exception handler. In this state, it knows that it is safe to vector to the handler directly without the need to perform any stack operations (pop the old state and push the current state) and this cuts the overhead down to 6 cycles.

The thorough explanation with a timing diagram can be found in chapter 5.6 of the CortexM3 Technical Reference Manual which you can download from ARM's web site here.

Post edited by: LMI Dave, at: 2008/09/25 08:26

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