Product Features

32-Bit RISC Performance

• 50-MHz operation with 32-bit ARM® Cortex™-M3 architecture
• Thumb®-compatible Thumb-2-only instruction set, with hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling
• 27 interrupt channels with eight priority levels
• Memory protection unit (MPU) provides a privileged mode for protected operating system functionality
• Unaligned data access enables data to be efficiently packed into memory
• Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control

• 128 KB single-cycle flash with two forms of flash protection on a 2-KB block basis
  • User-managed flash block protection on a 2-KB block basis
  • User-managed flash data programming
  • User-defined and managed flash-protection block
• 32 KB single-cycle SRAM
• Pre-programmed ROM containing the Stellaris® family peripheral driver library (DriverLib) and Stellaris® boot loader

• Developed and tested by ARM
• Up to a maximum of 32 configurable DMA channels, each with dedicated handshake signals and configurable priority levels
• Supports memory-to-memory, memory-to-peripheral, and peripheral-to-memory transfers
• Supports DMA transfers using data widths of 8, 16, or 32-bits
• Supports USB, UART, and SSI
• Compatible with the AMBA AHB-Lite protocol
• Number of transfers in each DMA cycle is programmable in binary steps from 1 to 1024
• Each DMA channel has separate outputs to indicate when a DMA cycle is active or complete

• Three fully programmable 16C550-type UARTs
• Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable baud-rate generator allowing speeds up to up to 3.125 Mbps

• Single- and differential-input configurations
• Eight 10-bit channels (inputs) when used as single-ended inputs
• Sample rate of 500 thousand samples/second
• On-chip temperature sensor

• Two I2C modules
• Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode
• Interrupt generation
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

• 0-33 GPIOs, depending on configuration
• 5-V-tolerant input/outputs
• Programmable interrupt generation as either edge-triggered or level-sensitive
• Low interrupt latency; as low as 6 cycles and never more than 12 cycles
• Bit masking in both read and write operations through address lines
• Can initiate an ADC sample sequence

• On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
• Battery-backed hibernation module with real-time clock and 256-bytes of non-volatile memory
• Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits
• Low-power options on controller: Sleep and Deep-sleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• On-chip temperature sensor

• Power-on reset (POR)
• Reset pin assertion
• Brown-out (BOR) detector alerts to system power drops
• Software reset
• Watchdog timer reset
• Internal low drop-out (LDO) regulator output goes unregulated

• Six reset sources
• Programmable clock source control
• Clock gating to individual peripherals for power savings
• IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
• Debug access via JTAG and Serial Wire interfaces
• Full JTAG boundary scan

• 64-pin RoHS-compliant LQFP package
  • Industrial-range (-40°C to +85°C)