Product Features

32-Bit RISC Performance

• 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
• 50-MHz operation with 32-bit ARM® Cortex™-M3 architecture
• System timer (SysTick) provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
• Thumb®-compatible Thumb-2-only instruction set, with hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) provides deterministic interrupt handling
• 31 interrupts with eight priority levels
• Memory protection unit (MPU) provides a privileged mode for protected operating system functionality
• Unaligned data access enables data to be efficiently packed into memory
• Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control

• 256 KB single-cycle flash
  • User-managed flash block protection on a 2-KB block basis
  • User-managed flash data programming
  • User-defined and managed flash-protection block
• 64 KB single-cycle SRAM

• Three general-purpose timers, each configurable as one 32-bit or two 16-bit timers
• Real-Time Clock (RTC) capability
• 24-bit system (SysTick) timer
• 32-bit watchdog timer

• Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timer/counters. Each GPTM can be configured to operate independently as timers or event counters (eight total): as a single 32-bit timer (four total), as one 32-bit Real-Time Clock (RTC) to event capture, for Pulse Width Modulation (PWM), or to trigger analog-to-digital conversions
• 32-bit Timer modes
  • Programmable one-shot timer
  • Programmable periodic timer
  • Real-Time Clock when using an external 32.768-KHz clock as the input
  • User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug
  • ADC event trigger
• 16-bit Timer modes
  • General-purpose timer function with an 8-bit prescaler
  • Programmable one-shot timer
  • Programmable periodic timer
  • User-enabled stalling when the controller asserts CPU Halt flag during debug
  • ADC event trigger
• 16-bit Input Capture modes
  • Input edge count capture
  • Input edge time capture
• 16-bit PWM mode
  • Simple PWM mode with software-programmable output inversion of the PWM signal

• 32-bit down counter with a programmable load register
• Separate watchdog clock with an enable
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic with an enable/disable
• User-enabled stalling when the controller asserts the CPU Halt flag during debug

• Synchronous serial interface (SSI) with master and slave modes for SPI, MICROWIRE, or TI synchronous serial
• I2C interface (master and slave)
• Two fully programmable 16C550-type UARTs with IrDA support

• Master or slave operation
• Programmable clock bit rate and prescale
• Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
• Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces
• Programmable data frame size from 4 to 16 bits
• Internal loopback test mode for diagnostic/debug testing

• Two fully programmable 16C550-type UARTs with IrDA support
• Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable baud-rate generator with fractional divider
• Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• False-start-bit detection
• Line-break generation and detection

• Single- and differential-input configurations
• Four 10-bit channels (inputs) when used as single-ended inputs
• Sample rate of one million samples/second
• Flexible, configurable analog-to-digital conversion
  • Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs
  • Each sequence triggered by software or internal event (timers, analog comparators, PWM or GPIO)
• On-chip temperature sensor

• One integrated analog comparator
• Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample sequence
• Compare external pin input to external pin input or to internal programmable voltage reference

• Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode
• Interrupt generation
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

• Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator, and a dead-band generator
• One 16-bit counter
  • Runs in Down or Up/Down mode
  • Output frequency controlled by a 16-bit load value
  • Load value updates can be synchronized
  • Produces output signals at zero and load value
• Two PWM comparators
  • Comparator value updates can be synchronized
  • Produces output signals on match
• PWM generator
  • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals
  • Produces two independent PWM signals
• Dead-band generator
  • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge
  • Can be bypassed, leaving input PWM signals unmodified
• Flexible output control block with PWM output enable of each PWM signal
  • PWM output enable of each PWM signal
  • Optional output inversion of each PWM signal (polarity control)
  • Optional fault handling for each PWM signal
  • Synchronization of timers in the PWM generator blocks
  • Synchronization of timer/comparator updates across the PWM generator blocks
  • Interrupt status summary of the PWM generator blocks
• Can initiate an ADC sample sequence

• 27-56 GPIOs, depending on configuration
• 5-V-tolerant input/outputs
• Programmable interrupt generation as either edge-triggered or level-sensitive
• Fast toggle capable of a change every two clock cycles
• Bit masking in both read and write operations through address lines
• Can initiate an ADC sample sequence
• Programmable drive strength and slew-rate control
• Programmable control for GPIO pad configuration:
  • Weak pull-up or pull-down resistors
  • 2-mA, 4-mA, and 8-mA pad drive
  • Slew rate control for the 8-mA drive
  • Open drain enables
  • Digital input enables

• On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
• Battery-backed hibernation module with real-time clock and 256-bytes of non-volatile memory
• 3.3-V supply brown-out detection
• Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits
• Low-power options on controller: Sleep and Deep-sleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• 3.3-V supply brown-out detection and reporting via interrupt or reset

• Power-on reset (POR)
• Reset pin assertion
• Brown-out (BOR) detector alerts to system power drops
• Software reset
• Watchdog timer reset
• Internal low drop-out (LDO) regulator output goes unregulated

• Six reset sources
• Programmable clock source control
• Clock gating to individual peripherals for power savings
• IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
• Debug access via JTAG and Serial Wire interfaces
• Full JTAG boundary scan

• 100-pin RoHS-compliant LQFP package
  • Industrial-range (-40°C to +85°C)
  • Extended-range (-40°C to +105°C)
• 108-ball RoHS-compliant BGA package
  • Industrial-range (-40°C to +85°C)