LM3S102 Development Kit
LM3S102 Daughterboard Kit
LM3S811 Evaluation Kits

Product Features

• 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications
• Thumb®-compatible Thumb-2-only instruction set processor core for high code density
• 20-MHz operation
• Hardware-division and single-cycle-multiplication
• Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling
• 14 interrupt channels with eight priority levels
• Unaligned data access, enabling data to be efficiently packed into memory
• Atomic bit manipulation (bit-banding) delivers maximum memory utilization and streamlined peripheral control
• 8 KB single-cycle flash with two forms of flash protection on a 2-KB block basis
• 2 KB single-cycle SRAM General-Purpose Timers
• Two timers, each of which can be configured as a single 32-bit timer or as a dual 16-bit timer with capture and simple PWM modes
• Real-Time Clock (RTC) capability
• 32-bit down counter with a programmable load register
• Separate watchdog clock with an enable
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic with an enable/disable Synchronous Serial Interface (SSI)
• Programmable interface operation for Freescale SPI, National Semiconductor MICROWIRE™, or Texas Instruments synchronous serial
• Master or slave operation
• Fully programmable 16C550-type UART
• Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable baud-rate generator with fractional divider
• Configurable for output to drive an output pin or generate an interrupt
• Compare external pin input to external pin input or to internal programmable voltage reference
• Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode
• Interrupt generation
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode
• Up to 18 GPIOs, depending on user configuration
• Programmable interrupt generation as either edgetriggered or level-sensitive on all pins
• Programmable drive strength and slew rate
• Bit-masking in both read and write operations
• On-chip Linear Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
• Low-power options on processor: Sleep and Deepsleep modes
• Low-power options for peripherals: software controls shutdown of individual peripherals
• User-enabled LDO unregulated voltage detection and automatic reset
• 3.3-V supply brownout detection and reporting via interrupt or reset
• Power-on reset (POR)
• Reset pin assertion
• Brown-out (BOR) detector
• Software reset
• Watchdog timer reset
• Internal linear drop-out (LDO) regulator
• IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
• Debug access via JTAG and Serial Wire interfaces
• 28-pin RoHS-compliant SOIC package
  • Industrial-range (-40°C to +85°C)
  • Extended-range (-40°C to +105°C)